1. Field of the Invention
The present invention relates to a method of controlling the operation (writing, erasing, and reading) of a semiconductor memory device configured by a plurality of non-volatile semiconductor memory chips.
2. Description of the Prior Art
In recent years, along with the wide spread of such portable devices as portable personal computers (PCs) and portable telephones, non-volatile semiconductor memories including flash memories are widely watched as information storage media employed for those portable devices.
Flash memories are roughly classified into two types according to the accessing unit length; NOR flash memory and AND/NAND flash memory. The NOR flash memory can be accessed in bytes at random, although it is small in capacity, a few megabytes at the most. The AND/NAND flash memory can be accessed in sectors while it has a capacity of a few tens of megabytes; each sector has a capacity of a few hundreds to a few thousands of bytes. The AND/NAND flash memory, which is a large capacity flash memory, is suitable as storages for which both low bit cost and sequential access performance are considered more important than random access performance in bytes. Card type semiconductor memory devices that employ the large capacity flash memories are now being manufactured by many corporations. A card type semiconductor memory device usually includes a plurality of flash memory chips to provide a larger capacity than that of the device itself. FIG. 1 shows a system that employs such a semiconductor memory device. A host system 1 is, for example, a personal computer or digital camera. A semiconductor memory device 2 is connected to the host system 1 and writes/reads information according to the commands received from the host system 1. The semiconductor memory device 2 is configured by a controller for controlling itself, an input/output interface 4 enabling commands and data to be sent/received between the host system 1 and the controller 3, a buffer memory 5, and a plurality of flash memory chips 6 for storing information. The controller 3 analyzes commands received from the host system 1 to control the flash memory chips 6 according to the analysis result and write/read information therein/therefrom. At this time, the controller 3 also erases information from each flash memory chip 6 as needed.
Next, a description will be made for the I/O interface 4 of the flash memory chips 6. Unlike other memories, the large capacity flash memory chip 6 usually has no address terminal. The flash memory chip 6 accesses each sector to perform command input, address input, and data input/output through a common I/O terminal in a time sharing manner in accordance with a procedure predetermined for itself separately. Generally, the large capacity flash memory chip performs an input/output operation in units of eight bits. A 20 MHz I/O clock is used for most of the memories. The large capacity flash memory chip has a plurality of input terminals used for controlling the protocol. The High/Low levels of those input terminals can be combined in various ways to switch among such operations as command input, address input, and data input/output.
FIGS. 52 through 54 show how to access such a large capacity flash memory chip. To simplify the description, the protocol control signal will be omitted and only the access procedure concept will be described here. Hereinafter, the description will be made on the assumption that the I/O bus is eight bits in width, the I/O clock is 20 MHz, the command input cycle is one cycle, the sector address input cycle is two cycles, and the sector size is 2112 bytes.
At first, the writing procedure will be described with reference to FIG. 54. Writing is done sequentially in the order of write command input CMD(W), write sector address input ADR, data input for one sector TR, write start command input CMD(SW), write end wait BUSY, and status read ST. When one sector data input ends, the inputted data is just stored in the buffer memory in the flash memory chip and not written in any memory cell therein yet. Writing in each memory cell in a specified sector starts at a write start command input. The flash memory chip disables simultaneous processing of two commands. When the next command is inputted just after the first one, the next write command is forced to wait for the completion of the preceding write command processing. And, after the flash memory is used for a certain time, the memory cells are degraded, thereby some sectors in the memory come to be disabled for correct writing. Consequently, the status of the flash memory chip is usually read after writing/erasing to/from each memory sector so as to check if the command processing is terminated normally therein. If the writing fails, the data is written in another sector (replacement processing). Each processing time in the above writing will become roughly as follows; the CMD(W) is 50 ns, the SDR is 100 ns, the TR is 110 xcexcs, the CMD(WS) is 50 ns, the BUSY is 2 ms, and the ST is 50 ns.
Next, how to erase information from the large capacity flash memory chip will be described with reference to FIG. 55. Erasing is performed sequentially in order of erase command input CMD(E), target sector address input ADR, erase start command input CMD(SE), wait for completion BUSY, and status read ST. Erasing from a memory cell in a specified sector starts at an erase start command input. Similarly to the writing described above, the next command input to the large capacity flash memory chip is forced to wait until the preceding erase command processing ends. And, similarly to the writing, the status of the large capacity flash memory chip is read usually after erasing of data from each memory sector to check if the command processing is terminated normally therein. When the erasing fails, the sector is registered as a defective one and replaced with another. Each processing time in the above erasing will become roughly as follows; the CMD(E) is 50 ns, the ADR is 100 ns, the CMD(ES) is 50 ns, the BUSY is 1 ms, and the ST is 50 ns.
Next, how to read information from the large capacity flash memory chip will be described with reference to FIG. 56. Reading is performed sequentially in order of read command input CMD (R), target sector address input ADR, wait for reading to be prepared BUSY, and data read (output) TR. Reading (transferring) data from a memory cell in a specified sector provided in a chip to the buffer memory in the large capacity flash memory chip starts at a sector address input, concretely when the read data is transferred completely to the buffer memory provided in the large capacity flash memory chip. Each processing time in the above reading will become roughly as follows; the CMD(R) is 50 ns, the ADR is 100 ns, the TR is 110 xcexcs, and the BUSY is 50 xcexcs.
In a semiconductor memory device configured by some flash memory chips, data is divided into a plurality of data blocks and stored in a plurality of flash memory chips so as to improve the sequential access performance. In other words, processings are performed in a plurality of flash memory chips in parallel to improve the practical sequential access performance.
Hereinafter, a conventional writing method employed for a semiconductor memory device configured by four flash memory chips will be described with reference to some drawings.
FIG. 57 shows the conventional writing method described on the time axis in a case in which the data size is assumed as sector size xc3x974. Data D is divided into data blocks D0 to D3, each having the same size as the sector size. The data blocks are written in different flash memory chips. In this case, the data block D0 is written in the large capacity flash memory chip 0, the data block D1 is written in the large capacity flash memory chip 1, the data block D2 is written in the large capacity flash memory chip 2, and the data block D3 is written in the large capacity flash memory chip 3 respectively. The CMD(W) denotes a write command input time, the ADRn denotes an input time of an address ADR assigned to each large capacity flash memory chip, the TR(Dn) denotes a data block Dn input time, the CMD(WS) denotes a write start command input time, and the TCxe2x80x94BUSY denotes a time for writing data inputted to the large capacity flash memory chip in a memory cell provided therein. At first, a write command, an address, a data block, and a write start command are inputted to the large capacity flash memory chip 0 respectively. Hereinafter, the above inputs are repeated sequentially for each of the remaining large capacity flash memory chips 1 to 3.
The official gazette of JP-A No.H11-273370 discloses a method for performing the write command input, the address ADR input, and the write start command input for all of the chips simultaneously by assuming ADR0 to ADR3 as the same address ADR, since the large capacity flash memory chips are all connected to a common bus.
FIG. 58 shows a conventional erasing method described on the time axis. The method erases data from addresses ADR0 to ADR3 specified in the large capacity flash memory chips 0 to 3. The CMD(E) denotes an erase command input time, the ADRn denotes an input time of an address ADR assigned to each of the large capacity flash memory chips, the CMD(ES) denotes an erase start command input time, and the TCxe2x80x94BUSY denotes a time for erasing data from a memory cell corresponding to an address specified for ADR. At first, an erase command, an address, and an erase start command are inputted to the large capacity flash memory chip 0 respectively. Hereinafter, the above inputs are repeated sequentially for each of the remaining large capacity flash memory chips 1 to 3.
The official gazette of JP-A No. H11-273370 discloses a method for performing the erase command input, the address ADR input, and the erase start command input for all of the chips 1 to 3 simultaneously by assuming ADR0 to ADR3 as the same address ADR, since the large capacity flash memory chips are all connected to a common bus.
FIG. 59 shows a conventional reading method described on the time axis. This method is used for a case in which the data size becomes sector size x 4. Data D is divided into data blocks D0 to D3, each having the same size as the sector size. The data blocks are written in different flash memory chips. In this case, the data block D0 is written in the large capacity flash memory chip 0, the data block D1 is written in the large capacity flash memory chip 1, the data block D2 is written in the large capacity flash memory chip 2, and the data block D3 is written in the large capacity flash memory chip 3 respectively. The CMD(R) denotes a read command input time, the ADRn denotes a time for inputting an address ADR to each large capacity flash memory chip, in which a data block Dn is already written. The TR(Dn) denotes a data block Dn reading time, and the TCxe2x80x94BUSY denotes a time of preparing for reading a data block from a large capacity flash memory chip in response to an inputted read command. At first, a read command and an address are inputted sequentially to the large capacity flash memory chip 0. Hereinafter, the above inputs are repeated sequentially for each of the remaining large capacity flash memory chips 1 to 3. The reading of a data block from a large capacity flash memory chip begins after all of the chips get ready to be read.
The official gazette of JP-A No. H11-273370 discloses a method for performing the read command input and the address ADR input to all of the chips 0 to 3 simultaneously by assuming ADR0 to ADR3 as the same address ADR, since the large capacity flash memory chips are all connected to a common bus.
In a large capacity flash memory chip, the writing time, the erasing time, and the reading time required for each memory cell are varied among sectors. And, the conventional controlling method described above cannot smooth out the variation.
Under such circumstances, it is an object of the present invention to provide a method for controlling a plurality of non-volatile semiconductor memory chips so as to solve the above conventional problem. Concretely, the method controls the memory chips so that a write command is inputted to each of the plurality of non-volatile semiconductor memory chips simultaneously in the first step, the same memory address is inputted to each of those non-volatile semiconductor memory chips simultaneously in the second step, and one of the memory chips is selected and a data block and a write start command are inputted to the selected memory chip in the third step. After this, another chip is selected sequentially so that it is subjected to the processing in this third step. In the fourth step, it is determined that the write start command processing is terminated in the memory chip, then another chip is selected sequentially so that it is subjected to the processing in the fifth step and the command execution result is checked therein. When data is to be written in a plurality of different addresses specified in a plurality of non-volatile semiconductor memory chips, the writing method described above is repeated for each of those different addresses.
In another way, in the first step, a write command is inputted to each of a plurality of non-volatile semiconductor memory chips. In the second step, the same memory address is inputted to each of the plurality of memory chips. In the third step, one of the memory chips is selected so that a data block and a write start command are inputted to the chip, then the chip is changed to another sequentially to repeat the processing in this third step. Then, in the fourth step, each of the memory chips is checked for the completion of the write start command and the command execution result check separately. When data is to be written in a plurality of different addresses specified in a plurality of memory chips, the write command and the address are inputted to each of the memory chips separately in and after the second round.
When data is erased from a plurality of non-volatile semiconductor memory chips, an erase command is inputted to each of those chips simultaneously in the first step and the same memory address is inputted to each of those memory chips simultaneously in the second step. Then, in the third step, an erase start command is inputted to each of those memory chips simultaneously. In the fourth step, it is determined that the processing of the erase start command has ended in each of those memory chips. In the fifth step, the chip is changed over to another to check the command execution result therein. When data is erased from a plurality of different addresses, the above processings are repeated for each of those different addresses.
In another way, an erase command is inputted to a plurality of non-volatile semiconductor memory chips simultaneously in the first step and the same memory address is inputted to each of those memory chips simultaneously in the second step. And, in the third step, an erase start command is inputted to each of those memory chips simultaneously. In the fourth step, it is determined in each memory chip separately that the processing of the erase start command is ended, then the command execution result is checked therein. When data is to be erased from a plurality of different addresses, the erase command, the address, and the erase start command are inputted to each of the memory chips separately after the command execution result check.
When data is to be read from a plurality of non-volatile semiconductor memory chips, a read command is inputted to each of those memory chips simultaneously in the first step and the same memory address is inputted to each of those memory chips simultaneously in the second step. Then, in the third step, it is determined that all the memory chips are ready to be read. In the fourth step, one of those memory chips is selected and one data block is read from the selected chip, then the memory chip is changed to another sequentially to repeat the processing in this third step. When data is to be read from a plurality of different addresses, the above processings are repeated for each of the different addresses.
In another way, a read command is inputted to a plurality of non-volatile semiconductor memory chips simultaneously in the first step and the same memory address is inputted to each of those memory chips simultaneously in the second step. Then, in the third step, it is determined in each memory chip separately that the memory chip is ready to be read, then one of the memory chips ready to be read is selected and one data block is read therefrom. After this, the memory chip is changed to another sequentially to repeat the processing in this third step. When data is to be read from a plurality of different addresses, the above processings are repeated so that the read command and each of the addresses are inputted to each of the memory chips just after the data block reading in the third step.